Configure and compile NuttX to the board: you can go legacy way with makefile or new way with CMake
Legacy way:
$ ./tools/configure.sh arcx-socket-grid:nsh
$ make -j
LD: nuttx
Memory region Used Size Region Size %age Used
flash: 94744 B 64 MB 0.14%
sram: 6588 B 512 KB 1.26%
itcm: 0 B 128 KB 0.00%
dtcm: 0 B 128 KB 0.00%
CP: nuttx.hexCMake way:
$ cmake -B build -DBOARD_CONFIG=arcx-socket-grid:nsh -GNinja
-- Configuring done (0.3s)
-- Generating done (0.1s)
-- Build files have been written to: /home/alan/nuttxspace/nuttx/build
$ cmake --build build
[7/9] Linking C executable nuttx
Memory region Used Size Region Size %age Used
flash: 94748 B 64 MB 0.14%
sram: 6572 B 512 KB 1.25%
itcm: 0 B 128 KB 0.00%
dtcm: 0 B 128 KB 0.00%
[9/9] Generating System.map
Now we need to flash the board, then set the boot pins to 1001:
Then use OpenOCD or JLinkExe to flash the firmware:
J-Link>con
Please specify device / core. <Default>: CORTEX-M33
Type '?' for selection dialog
Device>?
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "MIMXRT1052XXXXB" selected.
Connecting to target via SWD
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041, ADDR: 0x00000000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Cache: L1 I/D-cache present
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
[0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
[1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
[2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[2][1]: E0001000 CID B105E00D PID 000BB002 DWT
[2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[2][3]: E0000000 CID B105E00D PID 000BB001 ITM
[1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[1][2]: E0042000 CID B105900D PID 004BB906 CTI
[0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
[0][2]: E0043000 CID B105F00D PID 001BB101 TSG
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Memory zones:
Zone: "Default" Description: Default access mode
Cortex-M7 identified.Flashing:
J-Link>loadbin nuttx.hex, 0
'loadbin': Performing implicit reset & halt of MCU.
ResetTarget() start
Core did not halt on flash image verification. Assuming faulty flash settings.
Halting target manually.
ResetTarget() end - Took 320ms
Device specific reset executed.
AfterResetTarget() start
AfterResetTarget() end - Took 665us
Downloading file [nuttx.hex]...
J-Link: Flash download: Bank 0 @ 0x60000000: 1 range affected (262144 bytes)
J-Link: Flash download: Total: 3.502s (Prepare: 0.141s, Compare: 0.921s, Erase: 0.960s, Program: 0.483s, Verify: 0.926s, Restore: 0.069s)
J-Link: Flash download: Program speed: 529 KB/s
O.K.
J-Link>Now you need to change the boot pins to 1010 test the serial communication to NSH:
NuttShell (NSH) NuttX-12.10.0
nsh> uname -a
NuttX 12.10.0 7934a7dffd-dirty Jul 29 2025 13:10:03 arm arcx-socket-grid
nsh> ?
help usage: help [-v] [<cmd>]
. cp expr mkdir rmdir umount
[ cmp false mkrd set unset
? dirname fdinfo mount sleep uptime
alias df free mv source usleep
unalias dmesg help pidof test watch
basename echo hexdump printf time xd
break env kill ps true
cat exec pkill pwd truncate
cd exit ls rm uname
Builtin Apps:
dd nsh sh
nsh> free
total used free maxused maxfree nused nfree name
253500 5652 247848 6008 247848 21 1 Umem
nsh> ls /dev
/dev:
console
null
ttyS0
zero
nsh>