First configure SW7 to 1-ON, 2-ON, 3-ON, 4-OFF to avoid booting from external flash

Connect to JTAG cable on J21 in the board and run:

$ JLinkExe -if swd
SEGGER J-Link Commander V8.12a (Compiled Jan  9 2025 14:43:13)
DLL version V8.12a, compiled Jan  9 2025 14:42:08

Connecting to J-Link via USB...O.K.
Firmware: J-Link V11 compiled Dec  4 2024 17:53:35
Hardware version: V11.00
J-Link uptime (since boot): 0d 02h 22m 07s
S/N: 51005404
License(s): GDB
USB speed mode: High speed (480 MBit/s)
VTref=3.309V


Type "connect" to establish a target connection, '?' for help
J-Link>con
Please specify device / core. <Default>: MIMXRT1052XXXXB
Type '?' for selection dialog
Device>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "MIMXRT1052XXXXB" selected.


Connecting to target via SWD
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041, ADDR: 0x00000000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Cache: L1 I/D-cache present
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
[0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
[1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
[2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[2][1]: E0001000 CID B105E00D PID 000BB002 DWT
[2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[2][3]: E0000000 CID B105E00D PID 000BB001 ITM
[1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[1][2]: E0042000 CID B105900D PID 004BB906 CTI
[0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
[0][2]: E0043000 CID B105F00D PID 001BB101 TSG
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M7 identified.

J-Link>exec EnableEraseAllFlashBanks

J-Link>erase
No address range specified, 'Erase Chip' will be executed
'erase': Performing implicit reset & halt of MCU.
ResetTarget() start
Invalid flash header detected.
Target halted on flash header read.
ResetTarget() end - Took 120ms
Device specific reset executed.
AfterResetTarget() start
AfterResetTarget() end - Took 1.49ms
Erasing device...
J-Link: Flash download: Total time needed: 6.066s (Prepare: 0.167s, Compare: 0.000s, Erase: 5.831s, Program: 0.000s, Verify: 0.000s, Restore: 0.067s)
Erasing done.
J-Link>